15-硬件加速器

1 .CS5412/ Lecture 15 Hardware Accelerators Ken Birman CS5412 Spring 2019 http://www.cs.cornell.edu/courses/cs5412/2019sp 1

2 .In The early days, divide and Conquer Sufficed People broke web page computations into a first-tier, and then a bank of specialized -services optimized for highly parallel computation. Then sharded data and held it in memory, and created huge in-memory ( key,value ) layers. Batched programming techniques helped to amortize overheads, introducing delays, but weak cache consistency made some delay tolerable. http://www.cs.cornell.edu/courses/cs5412/2019sp 2

3 .Yet this turnED out to be expensive! Cloud computing companies began to look closely at their cost of operations, and use of energy An efficient cloud would fully utilize hardware but also minimize energy consumption. Those early steps were valuable and improved these metrics. But as the model matured, inefficiencies became more apparent A lot of resources were “owned” but not fully used. Time and money and energy was being spent waiting. http://www.cs.cornell.edu/courses/cs5412/2019sp 3

4 .Tension: Generality vs. Efficiency If we understand the workload deeply, we can often create extremely efficient specialized solutions, and could even create specialized chips that only include the exact hardware ideal for the task. But because computing workloads evolve, the solution would only be ideal for a few years, at best. Then it would start to seem inflexible and inefficient! Conversely, if we are overly general, we have this issue of copying data from place to place, and perhaps computing in less than ideal ways. http://www.cs.cornell.edu/courses/cs5412/2019sp 4

5 .Can we have it all? Modern datacenter hardware designers are asking: Can they create general purpose solutions in a normal way… … yet leverage specialized hardware where the benefits are large … in way that still can be upgraded periodically, or “repurposed” … and cut back on work done on the general purpose CPUs? http://www.cs.cornell.edu/courses/cs5412/2019sp 5

6 .Broad Hardware Trends There has always been a tradeoff between generality and efficiency A general purpose CPU has considerable advantages: Very cost-effective (high volume sales drive costs down) Highly performant (Moore’s law, until ~2010. Multicore+hyperthreading since then), flexible (lots of languages, computing models), familiar. Virtualization (VMs and containers) easily support sharing, so cloud can pack jobs to keep machines busy. http://www.cs.cornell.edu/courses/cs5412/2019sp 6 Amazon AWS server card

7 .But for certain tasks, specialized hardware is really needed Basically, these are devices that can either do something in hardware that normal CPU instructions don’t support (like direct operations on analog signals), or they can do parallel operations very efficiently. The parallel computing opportunity is the most intriguing, today. Someday, the analog dimension may get more attention. http://www.cs.cornell.edu/courses/cs5412/2019sp 7

8 .Accelerators: The Secret to Azure Performance! It is important to understand how vital these accelerators are in the cloud. People who pretend the cloud is just a rent-a-server model lose access to the accelerators (the vendors all have security features that block you). So because the accelerators are so amazing, you must use -services! http://www.cs.cornell.edu/courses/cs5412/2019sp 8

9 .How much speedup can we hope for? This was a debated topic in the 1970’s. Some people imagined that there could be magic ways to speed computation up, and the people building the actual chips needed to find a way to limit these unrealistic expectations! Eventually, Gene Amdahl found a way to explain the limits. http://www.cs.cornell.edu/courses/cs5412/2019sp 9

10 .AmdahL’s law Consider a computational task. We can express the code in terms of actions that can occur in parallel, and actions that can only be done sequentially. Measure the path-length of the sequential portion. This is performance-limiting for the whole computation! If F is the fraction of a calculation that is sequential, and (1-F) is the fraction that can be parallelized, then the maximum speed-up that can be achieved by using P processors is 1/(F+(1-F)/P).

11 .Examples If 90% of a calculation can be parallelized then the maximum speed-up on 2 processors is 1/(0.1+(1-0.1)/2) or 1.8 (i.e. investing twice as much hardware speeds the calculation up by almost 2x) … but with 10 processors, we only get a 5.2x speedup … on 20 processors, our speedup is 6.9x: diminishing returns! … on 1000 processors is 1/(0.1+(1-0.1)/1000) or 9.9x

12 .Highway analogy You buy a Tesla, take it out on California Route 101, and mash the “Ludicrous Acceleration” button. It can instantly accelerate to the speed of light! But you won’t get far… Your commute will be limited by “stragglers”.

13 .The other limiting factor: Heat! The clock rate might seem like a limiting factor, but a faster clock rate pumps more energy into the circuits and logic gates. The heat dissipated will be proportional to the square of the clock rate. In a parallel computing device, the whole surface might be active. So very fast clock rates make a chip run very hot . http://www.cs.cornell.edu/courses/cs5412/2019sp 13

14 .But if a device Gets too hot… Even a general purpose CPU is close to the heat-dissipation limits! Operating systems like Linux run the clock as slowly as possible for less active computing elements, and even disable hardware components that are not currently in use. This helps. But the clock rate on an accelerator might actually be lower than for a standard CPU! The (only) big win is parallelism. http://www.cs.cornell.edu/courses/cs5412/2019sp 14

15 .So acceleration options are limited to highly parallel tasks or “bump in the wire” Hardware might be able to perform highly parallel steps rapidly. We can also use hardware to reduce the work the host computer is doing. And if host computers can’t actually keep up with the network, we could perhaps wire the network directly to the hardware accelerator and if we’re lucky, the device might keep up with the incoming data! http://www.cs.cornell.edu/courses/cs5412/2019sp 15

16 .Acronym City! So now we’ll review a staggering list of incomprehensible 4-letter terms. You should memorize these to impress people. But we wouldn’t see them on exams! Sort of a “survey of the options” http://www.cs.cornell.edu/courses/cs5412/2019sp 16 Dude! They run Verilog on a Xilinx Vertix 5QV! Cool! Can’t wait to tell Mom!

17 .First, standard CPUs As you know, prior to 2010 Moore’s law was still “in control” and we had general purpose CPUs, with associated DRAM and caches, rotating disks. Around 2010 rotating disks were displaced by flash memory drives. These are actually kind of slow, so they often have some DRAM as a buffer. Simultaneously, chip designers invented branch prediction, data prefetching, speculative execution, hyperthreading, out-of-order exeuction http://www.cs.cornell.edu/courses/cs5412/2019sp 17

18 .After 2010 we saw NUMA Today, a cloud computing data center server probably has 12 or more cores per CPU chip, with DRAM organized into clusters, perhaps 4 chunks of DRAM with 3 cores each. (More cores/server are likely in the future) An on-board coherency protocol allows any core to access any memory, but the fastest data path is to the local DRAM. Then with container virtualization, we can run lots of programs per server. http://www.cs.cornell.edu/courses/cs5412/2019sp 18

19 .Storage devices are improving too… Disk I/O (even with flash SSD drives) often limits performance. New “non-volatile memory” options like Intel’s Optane NVMe are much faster. They use “phase change memory” technology. Today: NVMe is the new flash (somewhat expensive, but very fast) Flash is the new disk (slow, but cheaper and more capacity) Disk is the new tape (even slower, but massive capacity) http://www.cs.cornell.edu/courses/cs5412/2019sp 19

20 .Networks have evolved too The Network Interface Card (NIC) on your server now has a small operating system in it, and runs programs in C! (Written by the vendor) You can perform DMA transfers directly from machine to machine, not just from the network in and out of the machine as before. “Remote DMA” is like TCP (reliable, ordered, etc ) but the hardware does all the work. RDMA is way faster than TCP: we have RDMA at 200Gbps today, but the fastest TCP solutions are easily 4x or 6x slower. http://www.cs.cornell.edu/courses/cs5412/2019sp 20

21 .RDMA features With RDMA you can do some cool tricks Recall that with a NUMA machine, one core can access memory on any DRAM, so every machine shares the full memory pool. With RDMA, any core in the data center can potentially DMA transfer to memory anywhere else in the data center (but only if authorized). Moreover, RDMA allows direct access to variables or data structures hosted on a remote machine, too! (Again, only if authorized) This is like having a normal computer, but a million times more memory… http://www.cs.cornell.edu/courses/cs5412/2019sp 21

22 .GPU: A Common option Desktop computers generally have a multicore general-purpose computing infrastructure, but servers have a GPU that the general machine controls. The vendor creates a software library, so that a general purpose program can ask the GPU to perform a computation: DMA transfer to copy the data from general-purpose DRAM memory into the specialized GPU memory, which allows highly parallel access. GPU program executes to perform desired actions. Finally, the results are copied back to the general purpose host. http://www.cs.cornell.edu/courses/cs5412/2019sp 22 Titan GPU cluster

23 .GPU Programming is hard! Example of CUDA code There has been work on taking a general program coded in Java or C# and automatically finding “patterns” that can run on a GPU. Like a new compilation model in which the GPU offers special “instructions”. This gets to within 5x or 10x of hand-coded CUDA, but that isn’t enough http://www.cs.cornell.edu/courses/cs5412/2019sp 23

24 .Even using prebuilt GPU libraries is an ART If our goal was just to recolor photos, it might be easier. But graphics and vision algorithm often do very elaborate long sequences of matrix operations, and they may be designed with the specialized graphic display cards in mind (those cards can “see” data directly in memory, and can perform some operations on their own, like rescaling). As a result, hard-core gaming or imaging companies hire specialists. http://www.cs.cornell.edu/courses/cs5412/2019sp 24

25 .Limiting issues with GPU? First, heat: on a GPU chip, we do a form of single-instruction, multiple data processing (like “multiply every pixel by this value”). Expends a lot of energy But also copying: You also do a lot of copying from the general purpose host memory to the GPU memory, then back. (Hidden in GPU library, but costly). The GPU has “extra logic” not really needed for machine learning. If we could just power those features down, we could reduce these costs. http://www.cs.cornell.edu/courses/cs5412/2019sp 25

26 .“GPU For machine learning”? There has been more and more pressure to equip every computer in the cloud with a GPU, but this is very costly if those GPU units aren’t all in use. Still, many data centers take this approach. Google is betting that GPUs just aren’t cost-effective at scale and decided to strip the concept down to a minimum: TPUs == “Tensor Processing Units” http://www.cs.cornell.edu/courses/cs5412/2019sp 26

27 .TPU idea If the main demand for GPU is from machine learning, not full graphics code, we only need to support a subset of operations. Google focuses on “tensor arithmetic” (a tensor is just a matrix, but with d dimensions rather than just 1 or 2). Because less heat is produced by “ unnessary circuitry” we can reduce energy costs, or even run the clock a bit faster. http://www.cs.cornell.edu/courses/cs5412/2019sp 27 Google’s first TPU unit

28 .Tensor Flow language? Tensor flow is a version of Python extended to have a built-in concept of tensor objects and TPUs. Easy to express machine learning code this way. The typical program is a kind of data-flow graph in which nodes compute and these tensors “flow” from input sources to outputs. Mostly, tensor flow programs run on one NUMA machine, taking advantage of the attached TPU unit to accelerate the mathematical steps. http://www.cs.cornell.edu/courses/cs5412/2019sp 28

29 .Field Programmable Gate Arrays (FPGA) As you know, a CPU chip just maps instructions down to gate-level operations like AND, OR, XOR, NOT. Xilinx invented a way to take a chip and “download” a wiring diagram and a logic diagram to it. So you can “configure” your chip to have, say, an ARM or i86 processor on it. Of course that would be silly. But you can also design your own specialized chip, and in theory, it could do anything a GPU or TPU could do, or anything else, really. http://www.cs.cornell.edu/courses/cs5412/2019sp 29