1.Chapter 4 The Von Neumann Model & The LC3 Datapath & Control (These slides were developed in large part by Diana Palsetia at Upenn )
2.7 - 2 What Do We Know? Already discovered: Gates (AND, OR..) Combinational logic circuits (decoders, mux) Memory (latches, flip-flops) Sequential logic circuits (state machines) Simple processors (programmable traffic sign) What’s next? Apply all this to build a working processor
3.7 - 3 Von Neumann Model MEMORY MAR MDR INPUT Keyboard Mouse Scanner Disk OUTPUT Monitor Printer LED Disk PROCESSING UNIT ALU TEMP CONTROL UNIT PC IR
4.7 - 4 LC-3 Processor Von Nuemann Model CONTROL UNIT
5.7 - 5 LC-3 Data Path Filled arrow = info to be processed. Unfilled arrow = control signal. The data path of a computer is all the logic used to process information CONTROL UNIT
6.7 - 6 One More Device Tri-state buffer NOT an inverter! Device with a special output that can take a third state (i.e. besides 0 and 1) Allows wires to be “shared” Alternative to mux Only one source may drive at a time! Usually used to control data over a bus D Q E E D Q 1 0 0 1 1 1 0 0 Z 0 1 Z Z = “high impedance” state
7.7 - 7 Data Path Components Global bus Set of wires that carry 16-bit signals to many components Inputs to bus are controlled by triangle structure called tri-state devices Place signal on bus when enabled Only one (16-bit) signal should be enabled at a time Control unit decides which signal “drives” the bus Any number of components can read bus Register only captures bus data if write-enabled by the control unit Memory and I/O Control signals and data registers for memory and I/O devices Memory: MAR, MDR (also control signal for read/write) Input (keyboard): KBSR, KBDR Output (text display): DSR, DDR
8.4- 8 Memory 2 k x m array of stored bits Address unique ( k -bit) identifier of location Contents m -bit value stored in location Basic Operations: LOAD read a value from a memory location STORE write a value to a memory location • • • 0000 0001 0010 0011 0100 0101 0110 1101 1110 1111 00101101 10100010
9.7 - 9 Data Path Components (cont.) ALU Input: register file or sign-extended bits from IR (immediate field) Output: bus; used by… Condition code registers Register file Memory and I/O registers Register File Two read addresses, one write address (3 bits each) Input: 16 bits from bus Result of ALU operation or memory (or I/O) read Outputs: two 16-bit Used by ALU, PC, memory address Data for store instructions passes through ALU
10.ALU Combinational Logic 4- 10
11.Register File A bank of (nearby) memory 4- 11
12.7 - 12 Data Path Components (contd..) PC and PCMUX Three inputs to PC, controlled by PCMUX Current PC plus 1 (normal operation) Adder output (BR, JMP, …) Bus (TRAP) MAR and MARMUX Some inputs to MAR, controlled by MARMUX Zero-extended IR[7:0] (used for TRAP; more later) Adder output (LD, ST, …)
13.7 - 13 Data Path Components (cont..) Condition Code Logic Looks at value (from ALU) on bus and generates N, Z, P signals N,Z,P Registers are set only when control unit enables them Control Unit For each stage in instruction processing decides: Who drives the bus? Which registers are write enabled? Which operation should ALU perform? Lets Look at Instruction Processing next..
14.7 - 14 Instructions Fundamental unit of work Constituents Opcode : operation to be performed Operands : data/locations to be used for operation Encoded as a sequence of bits (just like data!) Sometimes have a fixed length ( e.g., 16 or 32 bits) Atomic: operation is either executed completely, or not at all
15.4- 15 Example: LC-3 ADD Instruction LC-3 has 16-bit instructions. Each instruction has a four-bit opcode, bits [15:12]. LC-3 has eight registers (R0-R7) for temporary storage. Sources and destination of ADD are registers. “Add the contents of R2 to the contents of R6, and store the result in R6.”
17.4- 17 Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer memory organization address space -- how may locations can be addressed? addressability -- how many bits per location? register set how many? what size? how are they used? instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language).
18.7 - 18 Instruction Processing DECODE instruction EVALUATE ADDRESS FETCH OPERANDS EXECUTE operation STORE result FETCH instruction from mem.
19.7 - 19 Instruction Processing: FETCH Idea Put next instruction in IR & increment PC Steps Load contents of PC into MAR Increment PC Send “read” signal to memory Read contents of MDR, store in IR EA OP EX S F D
20.7 - 20 FETCH in LC-3 Load PC into MAR (inc PC) Control Data CONTROL UNIT
21.7 - 21 FETCH in LC-3 Load PC into MAR Read Memory Control Data CONTROL UNIT
22.7 - 22 FETCH in LC-3 Load PC into MAR Read Memory Copy MDR into IR Control Data CONTROL UNIT
23.7 - 23 Instruction Processing: DECODE Identify opcode In LC-3, always first four bits of instruction 4-to-16 decoder asserts control line corresponding to desired opcode Identify operands from the remaining bits Depends on opcode e.g., for LDR, last six bits give offset e.g., for ADD, last three bits name source operand #2 EA OP EX S F D
24.7 - 24 DECODE in LC-3 CONTROL UNIT Decoding usually a part of the Control Unit but can be seperate
25.4- 25 Control Unit State Diagram The control unit is a state machine. Here is part of a simplified state diagram for the LC-3: A more complete state diagram is in Appendix C. It will be more understandable after Chapter 5.
26.7 - 26 Instruction Processing: EVALUATE ADDRESS Compute address For loads and stores For control-flow instructions Examples Add offset to base register (as in LDR) Add offset to PC (as in LD and BR) EA OP EX S F D
27.7 - 27 EVALUATE ADDRESS in LC-3 Load/Store CONTROL UNIT
28.7 - 28 Instruction Processing: FETCH OPERANDS Get source operands for operation Examples Read data from register file (ADD) Load data from memory (LDR) EA OP EX S F D
29.7 - 29 FETCH OPERANDS in LC-3 ADD CONTROL UNIT