堆栈

本文主要讲述了堆栈在计算机语言系统中的基本性质与运用。首先学习了LIFO存储结构,这种访问方式是定义堆栈,而不是具体实现。学习物理堆栈的概念,硬件实现和软件实现的定义。通过学习基本推送和流行代码了解堆栈算法。
展开查看详情

1.Chapter 10 And, Finally... The Stack

2.10- 2 Stacks A LIFO (last-in first-out) storage structure. The first thing you put in is the last thing you take out. The last thing you put in is the first thing you take out. This means of access is what defines a stack, not the specific implementation. Two main operations: PUSH: add an item to the stack POP: remove an item from the stack

3.10- 3 A Physical Stack Coin rest in the arm of an automobile First quarter out is the last quarter in. 1995 1996 1998 1982 1995 1998 1982 1995 Initial State After One Push After Three More Pushes After One Pop

4.10- 4 A Hardware Implementation Data items move between registers / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / Yes Empty: TOP #18 / / / / / / / / / / / / / / / / / / / / / / / / No Empty: TOP #12 #5 #31 #18 / / / / / / No Empty: TOP #31 #18 / / / / / / / / / / / / / / / / / / No Empty: TOP Initial State After One Push After Three More Pushes After Two Pops

5.10- 5 A Software Implementation Data items dont move in memory, just our idea about where the TOP of the stack is. / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / TOP / / / / / / / / / / / / / / / / / /

6.10- 6 Basic Push and Pop Code For our implementation, stack grows downward (when item added, TOS moves closer to 0) Push ADD R6, R6, #-1 ; decrement stack ptr STR R0, R6, #0 ; store data (R0) Pop LDR R0, R6, #0 ; load data from TOS ADD R6, R6, #1 ; decrement stack ptr

7.10- 7 Pop with Underflow Detection If we try to pop too many items off the stack, an underflow condition occurs. Check for underflow by checking TOS before removing data. Return status code in R5 (0 for success, 1 for underflow) POP LD R1, EMPTY ; EMPTY = -x4000 ADD R2, R6, R1 ; Compare stack pointer BRz FAIL ; with x3FFF LDR R0, R6, #0 ADD R6, R6, #1 AND R5, R5, #0 ; SUCCESS: R5 = 0 RET FAIL AND R5, R5, #0 ; FAIL: R5 = 1 ADD R5, R5, #1 RET EMPTY .FILL xC000

8.10- 8 Push with Overflow Detection If we try to push too many items onto the stack, an overflow condition occurs. Check for underflow by checking TOS before adding data. Return status code in R5 (0 for success, 1 for overflow) PUSH LD R1, MAX ; MAX = -x3FFB ADD R2, R6, R1 ; Compare stack pointer BRz FAIL ; with x3FFF ADD R6, R6, #-1 STR R0, R6, #0 AND R5, R5, #0 ; SUCCESS: R5 = 0 RET FAIL AND R5, R5, #0 ; FAIL: R5 = 1 ADD R5, R5, #1 RET MAX .FILL xC005

9.10- 8 Push with Overflow Detection If we try to push too many items onto the stack, an overflow condition occurs. Check for underflow by checking TOS before adding data. Return status code in R5 (0 for success, 1 for overflow) PUSH LD R1, MAX ; MAX = -x3FFB ADD R2, R6, R1 ; Compare stack pointer BRz FAIL ; with x3FFF ADD R6, R6, #-1 STR R0, R6, #0 AND R5, R5, #0 ; SUCCESS: R5 = 0 RET FAIL AND R5, R5, #0 ; FAIL: R5 = 1 ADD R5, R5, #1 RET MAX .FILL xC005

10.10- 10 Interrupt-Driven I/O (Part 2) Interrupts were introduced in Chapter 8. External device signals need to be serviced. Processor saves state and starts service routine. When finished, processor restores state and resumes program. Chapter 8 didn’t explain how (2) and (3) occur, because it involves a stack . Now, we’re ready… Interrupt is an unscripted subroutine call , triggered by an external event.

11.10- 11 Processor State What state is needed to completely capture the state of a running process? Processor Status Register Privilege [15], Priority Level [10:8], Condition Codes [2:0] Program Counter Pointer to next instruction to be executed. Registers All temporary state of the process that’s not stored in memory.

12.10- 12 Where to Save Processor State? Can’t use registers. Programmer doesn’t know when interrupt might occur, so she can’t prepare by saving critical registers. When resuming, need to restore state exactly as it was. Memory allocated by service routine? Must save state before invoking routine, so we wouldn’t know where. Also, interrupts may be nested – that is, an interrupt service routine might also get interrupted! Use a stack! Location of stack “hard-wired”. Push state to save, pop to restore.

13.10- 13 Supervisor Stack A special region of memory used as the stack for interrupt service routines. Initial Supervisor Stack Pointer (SSP) stored in Saved.SSP. Another register for storing User Stack Pointer (USP): Saved.USP. Want to use R6 as stack pointer. So that our PUSH/POP routines still work. When switching from User mode to Supervisor mode (as result of interrupt), save R6 to Saved.USP.

14.10- 14 Invoking the Service Routine – The Details If Priv = 0 (user), Saved.USP = R6, then R6 = Saved.SSP . Push PSR and PC to Supervisor Stack. Set PSR[15] = 0 (supervisor mode). Set PSR[10:8] = priority of interrupt being serviced. Set PSR[2:0] = 0. Set MAR = x01 vv , where vv = 8-bit interrupt vector provided by interrupting device (e.g., keyboard = x80). Load memory location (M[x01 vv ]) into MDR. Set PC = MDR; now first instruction of ISR will be fetched. Note: This all happens between the STORE RESULT of the last user instruction and the FETCH of the first ISR instruction.

15.10- 15 Returning from Interrupt Special instruction – RTI – that restores state. Pop PC from supervisor stack. (PC = M[R6]; R6 = R6 + 1) Pop PSR from supervisor stack. (PSR = M[R6]; R6 = R6 + 1) If PSR[15] = 0, R6 = Saved.USP . (If going back to user mode, need to restore User Stack Pointer.) RTI is a privileged instruction. Can only be executed in Supervisor Mode. If executed in User Mode, causes an exception . (More about that later.)

16.10- 16 Example (1) / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / x3006 PC Program A ADD x3006 Executing ADD at location x3006 when Device B interrupts. Saved.SSP

17.10- 17 Example (2) / / / / / / x3007 PSR for A / / / / / / / / / / / / x6200 PC R6 Program A ADD x3006 Saved.USP = R6. R6 = Saved.SSP. Push PSR and PC onto stack, then transfer to Device B service routine (at x6200). x6200 ISR for Device B x6210 RTI

18.10- 18 Example (3) / / / / / / x3007 PSR for A / / / / / / / / / / / / x6203 PC R6 Program A ADD x3006 Executing AND at x6202 when Device C interrupts. x6200 ISR for Device B AND x6202 x6210 RTI

19.10- 19 Example (4) / / / / / / x3007 PSR for A x6203 PSR for B x6300 PC R6 Program A ADD x3006 x6200 ISR for Device B AND x6202 ISR for Device C Push PSR and PC onto stack, then transfer to Device C service routine (at x6300). x6300 x6315 RTI x6210 RTI

20.10- 20 Example (5) / / / / / / x3007 PSR for A x6203 PSR for B x6203 PC R6 Program A ADD x3006 x6200 ISR for Device B AND x6202 ISR for Device C Execute RTI at x6315; pop PC and PSR from stack. x6300 x6315 RTI x6210 RTI

21.10- 21 Example (6) / / / / / / x3007 PSR for A x6203 PSR for B x3007 PC Program A ADD x3006 x6200 ISR for Device B AND x6202 ISR for Device C Execute RTI at x6210; pop PSR and PC from stack. Restore R6. Continue Program A as if nothing happened. x6300 x6315 RTI x6210 RTI Saved.SSP

22.10- 22 Exception: Internal Interrupt When something unexpected happens inside the processor, it may cause an exception. Examples: Privileged operation (e.g., RTI in user mode) Executing an illegal opcode Divide by zero Accessing an illegal address (e.g., protected system memory) Handled just like an interrupt Vector is determined internally by type of exception Priority is the same as running program