1.Chapter 8 I/O
2.8- 2 I/O: Connecting to Outside World So far, we’ve learned how to: compute with values in registers load data from memory to registers store data from registers to memory But where does data in memory come from? And how does data get out of the system so that humans can use it?
4.8- 4 I/O Controller Control/Status Registers CPU tells device what to do -- write to control register CPU checks whether task is done -- read status register Data Registers CPU transfers data to/from device Device electronics performs actual operation pixels to screen, bits to/from disk, characters from keyboard Graphics Controller Control/Status Output Data Electronics CPU display
5.8- 5 Programming Interface How are device registers identified? Memory-mapped vs. special instructions How is timing of transfer managed? Asynchronous vs. synchronous Who controls transfer? CPU ( polling ) vs. device ( interrupts )
6.8- 6 Memory-Mapped vs. I/O Instructions Instructions designate opcode(s) for I/O register and operation encoded in instruction Memory-mapped assign a memory address to each device register use data movement instructions (LD/ST) for control and data transfer
7.I/O Bus 8- 7
8.LC3 Memory 8- 8
9.8- 9 LC-3 Memory-mapped I/O (Table A.3) Asynchronous devices synchronized through status registers Polling and Interrupts the details of interrupts will be discussed in Chapter 10 Location I/O Register Function xFE00 Keyboard Status Reg (KBSR) Bit  is one when keyboard has received a new character. xFE02 Keyboard Data Reg (KBDR) Bits [7:0] contain the last character typed on keyboard. xFE04 Display Status Register (DSR) Bit  is one when device ready to display another char on screen. xFE06 Display Data Register (DDR) Character written to bits [7:0] will be displayed on screen.
10.8- 10 Simple Implementation: Memory-Mapped Input Address Control Logic determines whether MDR is loaded from Memory or from KBSR/KBDR.
11.8- 11 Input from Keyboard When a character is typed: its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero) the “ready bit” (KBSR) is set to one keyboard is disabled -- any typed characters will be ignored When KBDR is read: KBSR is set to zero keyboard is enabled KBSR KBDR 15 8 7 0 15 14 0 keyboard data ready bit
12.8- 12 Basic Input Routine new char? read character YES NO Polling POLL LDI R0, KBSRPtr BRzp POLL LDI R0, KBDRPtr ... KBSRPtr .FILL xFE00 KBDRPtr .FILL xFE04
13.8- 13 Output to Monitor When Monitor is ready to display another character: the “ready bit” (DSR) is set to one When data is written to Display Data Register: DSR is set to zero character in DDR[7:0] is displayed any other character data written to DDR is ignored (while DSR is zero) DSR DDR 15 8 7 0 15 14 0 output data ready bit
14.8- 14 Basic Output Routine screen ready? write character YES NO Polling POLL LDI R1, DSRPtr BRzp POLL STI R0, DDRPtr ... DSRPtr .FILL xFE04 DDRPtr .FILL xFE06
15.8- 15 Simple Implementation: Memory-Mapped Output Sets LD.DDR or selects DSR as input.
16.8- 16 Keyboard Echo Routine Usually, input character is also printed to screen. User gets feedback on character typed and knows its ok to type the next character. new char? read character YES NO screen ready? write character YES NO POLL1 LDI R0, KBSRPtr BRzp POLL1 LDI R0, KBDRPtr POLL2 LDI R1, DSRPtr BRzp POLL2 STI R0, DDRPtr ... KBSRPtr .FILL xFE00 KBDRPtr .FILL xFE02 DSRPtr .FILL xFE04 DDRPtr .FILL xFE06
18.8- 18 Transfer Control Who determines when the next data transfer occurs? Polling CPU keeps checking status register until new data arrives OR device ready for next data “Are we there yet? Are we there yet? Are we there yet?” Interrupts Device sends a special signal to CPU when new data arrives OR device ready for next data CPU can be performing other tasks instead of polling device. “Wake me when we get there.”
19.8- 19 Interrupt-Driven I/O External device can: Force currently executing program to stop; Have the processor satisfy the device’s needs; and Resume the stopped program as if nothing happened. Why? Polling consumes a lot of cycles, especially for rare events – these cycles can be used for more computation. Example: Process previous input while collecting current input. (See Example 8.1 in text - page 221.)
20.8- 20 Interrupt-Driven I/O To implement an interrupt mechanism, we need: A way for the I/O device to signal the CPU that an interesting event has occurred. A way for the CPU to test whether the interrupt signal is set and whether its priority is higher than the current program. Generating Signal Software sets "interrupt enable" bit in device register. When ready bit is set and IE bit is set, interrupt is signaled. KBSR 15 14 0 ready bit 13 interrupt enable bit interrupt signal to processor
21.8- 21 Priority Every instruction executes at a stated level of urgency. LC-3: 8 priority levels (PL0-PL7) Example: Payroll program runs at PL0. Nuclear power correction program runs at PL6. It’s OK for PL6 device to interrupt PL0 program, but not the other way around. Priority encoder selects highest-priority device, compares to current processor priority level, and generates interrupt signal if appropriate.
22.8- 22 Testing for Interrupt Signal CPU looks at signal between EXECUTE and FETCH phases. If not set, continues with next instruction. If set, transfers control to interrupt service routine. Fetch interrupt signal? Transfer to ISR NO YES More details in Chapter 10. Decode Execute