多周期处理器的设计

本文主要学习了多周期处理器的设计。首先学习单周期处理器的设计与应用,指令存取部件的基本性质以及它的主控单元构成。然后讨论了单周期处理器的缺点,从而引入多周期处理器的设计,讲述如何实现用多周期处理器来解决这些缺点。在这当中,加载指令的五个步骤尤为重要。
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1. ECE4680 Computer Organization and Architecture Designing a Multiple Cycle Processor ECE4680 Multipath.1 2002-3-31 A Single Cycle Processor ALUop ALU ALUctr RegDst 3 func Control op Main 3 ALUSrc Instr<5:0> 6 6 Control Instr<31:26> : Branch Instruction<31:0> Instruction <21:25> <16:20> <11:15> <0:15> Jump Fetch Unit Rd Rt RegDst Clk 1 Mux 0 Rs Rt Rt Rs Rd Imm16 RegWr 5 5 5 ALUctr busA Zero MemWr MemtoReg Rw Ra Rb busW 32 ALU 32 32-bit 32 0 Registers busB 0 32 Mux Clk Mux 32 32 WrEn Adr 1 Extender 1 Data In 32 imm16 Data 32 Instr<15:0> 16 Memory Clk ALUSrc ExtOp ECE4680 Multipath.2 2002-3-31

2. Concepts Functional/Combinational Components Sate/Memory/Sequential Datapath Connections Bus for data Control Signals instruction Control signals ECE4680 Multipath.3 2002-3-31 Instruction Fetch Unit Why does the PC use 30-bit counter? 30 Addr<31:2> PC<31:28> 30 Addr<1:0> “00” Target 4 1 Instruction Instruction<25:0> 30 Mux 26 Memory PC 0 30 Adder 0 32 30 Mux “1” Adder 1 Jump Instruction<31:0> Clk 30 SignExt imm16 30 Instruction<15:0> 16 Branch Zero ECE4680 Multipath.4 2002-3-31

3. The Main Control op<5> .. op<5> .. op<5> .. op<5> .. op<5> .. op<5>.. <0> <0> <0> <0> <0> op<0> R-type ori lw sw beq jump RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0> ECE4680 Multipath.5 2002-3-31 Drawbacks of this Single Cycle Processor °Long cycle time: • Cycle time must be long enough for the load instruction: - PC’s Clock -to-Q + - Instruction Memory Access Time + - Register File Access Time + - ALU Delay (address calculation) + - Data Memory Access Time + - Register File Setup Time + - Clock Skew °Cycle time is much longer than needed for all other instructions. Examples: • R-type instructions do not require data memory access • Jump does not require ALU operation nor data memory access ECE4680 Multipath.6 2002-3-31

4. Overview of a Multiple Cycle Implementation °The root of the single cycle processor’s problems: • The cycle time has to be long enough for the slowest instruction °Solution: • Break the instruction into smaller steps • Execute each step (instead of the entire instruction) in one cycle - Cycle time: time it takes to execute the longest step, not the longest instruction - Keep all the steps to have similar length • This is the essence of the multiple cycle processor °The advantages of the multiple cycle processor: • Cycle time is much shorter • Different instructions take different number of cycles to complete - Load takes five cycles - Jump only takes three cycles • Allows a functional unit to be used more than once per instruction - Adder + ALU - Instruction mem + Data mem ECE4680 Multipath.7 2002-3-31 The Five Steps of a Load Instruction Instruction Fetch Instr Decode / Address Data Memory Reg Wr Reg. Fetch Clk Clk-to-Q PC Old Value New Value Instruction Memory Access Time Rs, Rt, Rd, Old Value New Value Op, Func 1 Delay through Control Logic ALUctr Old Value New Value ExtOp Old Value New Value ALUSrc Old Value New Value Register File Write Time RegWr Old Value New Value 2 Register File Access Time busA Old Value New Value Delay through Extender & Mux 3 busB Old Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busW Old Value New ECE4680 Multipath.8 2002-3-31

5. Register File & Memory Write Timing: Ideal vs. Reality °In previous lectures for 1-cycle machine, register file and memory are simplified: WrEn • Write happens at the clock tick Adr 32 Ideal • Address, data, and write enable must be stable one “set-up” time before the clock tick Memory Din Dout 32 32 In real life for m-cycle machines: Clk • Neither register file nor ideal memory has the clock input • The write path is a combinational logic delay path: - Write enable goes to 1 and Din settles down WrEn Adr - Memory write access delay 32 Ideal - Din is written into mem[address] Memory • Important: Address and Data must be Din Dout 32 32 stable BEFORE Write Enable goes to 1 ECE4680 Multipath.9 2002-3-31 Race Condition Between Address and Write Enable What is race condition? °This “real” (no clock input) register file may not work reliably in the single cycle processor because: Ra RegWr 5 Rb busA • We cannot guarantee Rw will 5 be stable BEFORE RegWr = 1 Reg File 32 Rw busB • There is a “race” between Rw (address) 5 32 and RegWr (write enable) busW 32 °The “real” (no clock input) memory may not work WrEn reliably in the single cycle processor because: Adr 32 Ideal • We cannot guarantee Address will be stable BEFORE WrEn = 1 Memory • There is a race between Adr and WrEn Din Dout 32 32 ECE4680 Multipath.10 2002-3-31

6. How to Avoid this Race Condition? °Solution for the multiple cycle implementation: • Make sure Address is stable by the end of Cycle N • Assert Write Enable signal ONE cycle later at Cycle (N + 1) • Address cannot change until Write Enable is disasserted ECE4680 Multipath.11 2002-3-31 Dual-Port Ideal Memory °Dual Port Ideal Memory • Independent Read (RAdr, Dout) and Write (WAdr, Din) ports • Read and write (to different location) can occur at the same instruction cycle °Read Port is a combinational path: MemWr • Read Address Valid --> • Memory Read Access Delay --> 00 • Data Out Valid RAdr<1:0> <31:2> 30 °Write Port is also a combinational path: Ideal 32 Memory • MemWrite = 1 --> WrAdr Din Dout • Memory Write Access Delay --> 32 32 • Data In is written into location[WrAdr] ECE4680 Multipath.12 2002-3-31

7. Instruction Fetch Cycle: In the Beginning °Every cycle begins right AFTER the clock tick: • mem[PC] PC<31:0> + 4 Clk One “Logic” Clock Cycle You are here! PCWr=? PC 32 MemWr=? IRWr=? 32 ALU 32 Instruction Reg Clk RAdr 4 32 32 Ideal Memory ALU WrAdr 32 Control 32 Dout Din 32 ALUop=? 32 Clk ECE4680 Multipath.13 2002-3-31 Instruction Fetch Cycle: The End °Every cycle ends AT the next clock tick (storage element updates): • IR mem[PC] PC<31:0> PC<31:0> + 4 Clk One “Logic” Clock Cycle You are here! PCWr=1 PC 32 MemWr=0 IRWr=1 32 ALU 32 Instruction Reg Clk RAdr 4 32 32 Ideal Memory ALU 32 WrAdr 32 Control Din Dout 32 32 ALUOp = Add Clk ECE4680 Multipath.14 2002-3-31

8. Instruction Fetch Cycle: Overall Picture Ifetch Why do we need PCWr ALUOp=Add unlike in 1-cycle machine? 1: PCWr, IRWr x: PCWrCond RegDst, Mem2R Others: 0s PCWr=1 PCWrCond=x PCSrc=0 BrWr=0 Zero IorD=0 MemWr=0 IRWr=1 ALUSelA=0 1 Target Mux 32 32 PC 0 0 32 Zero Mux Instruction Reg 0 Mux 32 RAdr 32 ALU busA 1 32 Ideal 32 1 4 0 Memory WrAdr 32 32 32 1 32 Din Dout busB 32 32 2 3 ALU Control ALUSelB=00 ALUOp=Add ECE4680 Multipath.15 2002-3-31 Register Fetch / Instruction Decode °busA RegFile[rs] ; busB RegFile[rt] ; °ALU is not being used: ALUctr = xx PCWr=0 PCWrCond=0 Zero PCSrc=x IorD=x MemWr=0 IRWr=0 RegDst=x RegWr=0 ALUSelA=x 1 Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 3 Control Go to the Op 6 Imm ALUSelB=xx Control Func 6 16 ALUOp=xx ECE4680 Multipath.16 2002-3-31

9. Register Fetch / Instruction Decode (Continue) Rfetch/Decode °busA Reg[rs] ; busB Reg[rt] ; ALUOp=Add Why can we not further send target 1: BrWr, ExtOp address to PC? °Target PC + SignExt(Imm16)*4 ALUSelB=10 (speculative calculation) x: RegDst, PCSrc IorD, MemtoReg PCWr=0 PCWrCond=0 Others: 0s Zero PCSrc=x BrWr=1 IorD=x MemWr=0 IRWr=0 RegDst=x RegWr=0 ALUSelA=0 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 3 << 2 Control Beq Rtype Control Op 6 Imm Ori Func ALUSelB=10 Extend Memory 6 16 32 ALUOp=Add : ExtOp=1 ECE4680 Multipath.17 2002-3-31 Branch Completion BrComplete °if (busA == busB) ALUOp=Sub • PC Target ALUSelB=01 x: IorD, Mem2Reg RegDst, ExtOp 1: PCWrCond ALUSelA PCWr=0 PCWrCond=1 PCSrc Zero PCSrc=1 BrWr=0 IorD=x MemWr=0 IRWr=0 RegDst=x RegWr=0 ALUSelA=1 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 3 << 2 Control Imm ALUSelB=01 Extend 16 32 ALUOp=Sub ExtOp=x ECE4680 Multipath.18 2002-3-31

10. Instruction Decode: We have a R-type! °Next Cycle: R-type Execution PCWr=0 PCWrCond=0 Zero PCSrc=x BrWr=1 IorD=x MemWr=0 IRWr=0 RegDst=x RegWr=0 ALUSelA=0 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 3 << 2 Control Beq Rtype Control Op 6 Imm Ori Func ALUSelB=10 Extend Memory 6 16 32 ALUOp=Add : ExtOp=1 ECE4680 Multipath.19 2002-3-31 R-type Execution RExec 1: RegDst °ALU Output busA op busB ALUSelA ALUSelB=01 ALUOp=Rtype x: PCSrc, IorD PCWr=0 PCWrCond=0 MemtoReg PCSrc=x BrWr=0 ExtOp Zero IorD=x MemWr=0 IRWr=0 RegDst=1 RegWr=0 ALUSelA=1 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 1 Mux 0 3 << 2 Control Why not set RegDst=1 Imm 16 Extend at next cycle? 32 ALUOp=Rtype ExtOp=x MemtoReg=x ALUSelB=01 ECE4680 Multipath.20 2002-3-31

11. R-type Completion Rfinish ALUOp=Rtype °R[rd] <- ALU Output 1: RegDst, RegWr ALUselA ALUSelB=01 PCWr=0 PCWrCond=0 x: IorD, PCSrc PCSrc=x BrWr=0 ExtOp Zero IorD=x MemWr=0 IRWr=0 RegDst=1 RegWr=1 ALUSelA=1 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 1 Mux 0 3 << 2 Control Imm 16 Extend 32 ALUOp=Rtype ExtOp=x MemtoReg=0 ALUSelB=01 ECE4680 Multipath.21 2002-3-31 A Multiple Cycle Delay Path °There is no register to save the results between: • Register Fetch: busA Reg[rs] ; busB Reg[rt] • R-type Execution: ALU output busA op busB • R-type Completion: Reg[rd] ALU output Register here to save outputs of Rfetch? ALUselA IRWr=0 0 Register here to save Mux Rs Zero Instruction Reg Ra outputs of RExec? Rt 5 busA 32 1 ALU 32 Rb 5 Reg File 32 Rt 0 4 0 Mux Rw 32 Rd 1 32 busW busB 32 1 2 1 Mux 0 3 ALU Control ALUselB ALUOp ECE4680 Multipath.22 2002-3-31

12. A Multiple Cycle Delay Path (Continue) °Register is NOT needed to save the outputs of Register Fetch: • IRWr = 0: busA and busB will not change after Register Fetch °Register is NOT needed to save the outputs of R-type Execution: • busA and busB will not change after Register Fetch • Control signals ALUSelA, ALUSelB, and ALUOp will not change after R-type Execution • Consequently ALU output will not change after R-type Execution °In theory, you need a register to hold a signal value if: • (1) The signal is computed in one clock cycle and used in another. • (2) AND the inputs to the functional block that computes this signal can change before the signal is written into a state element. °You can save a register if Cond 1 is true BUT Cond 2 is false: • But in practice, this will introduce a multiple cycle delay path: - A logic delay path that takes multiple cycles to propagate from one storage element to the next storage element ECE4680 Multipath.23 2002-3-31 Pros and Cons of a Multiple Cycle Delay Path °A 3-cycle path example: • IR (storage) Reg File Read ALU Reg File Write (storage) °Advantages: • Register savings • We can share time among cycles: - If ALU takes longer than one cycle, still “a OK” as long as the entire path takes less than 3 cycles to finish 0 Mux Rs Zero Instruction Reg Ra Rt 5 busA 32 1 ALU 32 Rb 5 Reg File 32 Rt 0 4 0 Mux Rw 32 Rd 1 32 busW busB 32 1 2 1 Mux 0 3 ALU Control ALUselB ECE4680 Multipath.24 2002-3-31

13. Pros and Cons of a Multiple Cycle Delay Path (Continue) °Disadvantage: • Static timing analyzer, which ONLY looks at delay between two storage elements, will report this as a timing violation • You have to ignore the static timing analyzer’s warnings • But you may end up ignoring real timing violations • Always TRY to put in registers between cycles to avoid MCDP 0 Mux Rs Zero Instruction Reg Ra Rt 5 busA 32 1 ALU 32 Rb 5 Reg File 32 Rt 0 4 0 Mux Rw 32 Rd 1 32 busW busB 32 1 2 1 Mux 0 3 ALU Control ALUselB ECE4680 Multipath.25 2002-3-31 Instruction Decode: We have an Ori! °Next Cycle: Ori Execution PCWr=0 PCWrCond=0 Zero PCSrc=x BrWr=1 IorD=x MemWr=0 IRWr=0 RegDst=x RegWr=0 ALUSelA=0 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Intruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 3 << 2 Control Beq Rtype Control Op 6 Imm Ori Func ALUSelB=10 Extend Memory 6 16 32 ALUOp=Add : ExtOp=1 ECE4680 Multipath.26 2002-3-31

14. Ori Execution ALUOp=Or OriExec °ALU output busA or ZeroExt[Imm16] 1: ALUSelA ALUSelB=11 x: MemtoReg IorD, PCSrc PCWr=0 PCWrCond=0 PCSrc=x BrWr=0 Zero IorD=x MemWr=0 IRWr=0 RegDst=0 RegWr=0 ALUSelA=1 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 1 Mux 0 3 << 2 Control Imm 16 Extend 32 ALUOp=Or ExtOp=0 MemtoReg=x ALUSelB=11 ECE4680 Multipath.27 2002-3-31 Ori Completion OriFinish ALUOp=Or °Reg[rt] ALU output x: IorD, PCSrc ALUSelB=11 1: ALUSelA PCWr=0 PCWrCond=0 RegWr PCSrc=x BrWr=0 Zero IorD=x MemWr=0 IRWr=0 RegDst=0 RegWr=1 ALUSelA=1 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 1 Mux 0 3 << 2 Control Imm 16 Extend 32 ALUOp=Or ExtOp=0 MemtoReg=0 ALUSelB=11 ECE4680 Multipath.28 2002-3-31

15. Instruction Decode: We have a Memory Access! °Next Cycle: Memory Address Calculation PCWr=0 PCWrCond=0 Zero PCSrc=x BrWr=1 IorD=x MemWr=0 IRWr=0 RegDst=x RegWr=0 ALUSelA=0 1 Target Mux 32 32 PC 0 0 32 Rs Zero Mux Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 3 << 2 Control Beq Rtype Control Op 6 Imm Ori Func ALUSelB=10 Extend Memory 6 16 32 ALUOp=Add : ExtOp=1 ECE4680 Multipath.29 2002-3-31 Memory Address Calculation 1: ExtOp AdrCal ALUSelA ALUSelB=11 °ALU output busA + SignExt[Imm16] ALUOp=Add x: MemtoReg PCSrc PCWr=0 PCWrCond=0 PCSrc=x BrWr=0 Zero IorD=x MemWr=0 IRWr=0 RegDst=x RegWr=1 ALUSelA=1 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 1 Mux 0 3 << 2 Control Imm 16 Extend 32 ALUOp=Add ExtOp=1 MemtoReg=x ALUSelB=11 ECE4680 Multipath.30 2002-3-31

16. Memory Access for Store 1: ExtOp MemWr SWmem ALUSelA °mem[ALU output] busB ALUSelB=11 ALUOp=Add x: PCSrc,RegDst PCWr=0 PCWrCond=0 MemtoReg PCSrc=x BrWr=0 Zero IorD=x MemWr=1 IRWr=0 RegDst=x RegWr=0 ALUSelA=1 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 1 Mux 0 3 << 2 Control Imm 16 Extend 32 ALUOp=Add Keep ALUSelA, ALUSelB, ExtOp=1 MemtoReg=x ALUSelB=11 ALUOp same as previous cycle! ECE4680 Multipath.31 2002-3-31 Memory Access for Load 1: ExtOp LWmem ALUSelA, IorD ALUSelB=11 °Mem Dout mem[ALU output] ALUOp=Add x: MemtoReg PCSrc PCWr=0 PCWrCond=0 PCSrc=x BrWr=0 Zero IorD=1 MemWr=0 IRWr=0 RegDst=0 RegWr=0 ALUSelA=1 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 1 Mux 0 3 << 2 Control Imm 16 Extend 32 ALUOp=Add ExtOp=1 MemtoReg=x ALUSelB=11 ECE4680 Multipath.32 2002-3-31

17. Write Back for Load LWwr 1: ALUSelA RegWr, ExtOp °Reg[rt] Mem Dout MemtoReg ALUSelB=11 ALUOp=Add x: PCSrc PCWr=0 PCWrCond=0 IorD PCSrc=x BrWr=0 Zero IorD=x MemWr=0 IRWr=0 RegDst=0 RegWr=1 ALUSelA=1 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 1 Mux 0 3 << 2 Control Imm 16 Extend 32 ALUOp=Add ExtOp=1 MemtoReg=1 ALUSelB=11 ECE4680 Multipath.33 2002-3-31 Putting it all together: Multiple Cycle Datapath PCWr PCWrCond PCSrc BrWr Zero IorD MemWr IRWr RegDst RegWr ALUSelA 1 Target Mux 32 32 PC 0 0 32 Zero Mux Rs Instruction Reg 0 Ra Mux 32 RAdr Rt 5 32 ALU 32 Rb busA 1 32 Ideal 5 32 Reg File 1 Memory Rt 0 4 0 Mux WrAdr 32 Rw 32 32 Rd 1 32 Din Dout busW busB 32 1 2 32 ALU 1 Mux 0 3 << 2 Control Imm 16 Extend 32 ALUOp ExtOp MemtoReg ALUSelB ECE4680 Multipath.34 2002-3-31

18. Summary °Disadvantages of the Single Cycle Processor • Long cycle time • Cycle time is too long for all instructions except the Load °Multiple Cycle Processor: • Divide the instructions into smaller steps • Execute each step (instead of the entire instruction) in one cycle °Do NOT confuse Multiple Cycle Processor with Multiple Cycle Delay Path • Multiple Cycle Processor executes each instruction in multiple clock cycles • Multiple Cycle Delay Path: a combinational logic path between two storage elements that takes more than one clock cycle to complete °It is possible (desirable) to build a MC Processor without MCDP: • Use a register to save a signal’s value whenever a signal is generated in one clock cycle and used in another cycle later ECE4680 Multipath.35 2002-3-31 Putting it all together: Control State Diagram Ifetch Rfetch/Decode BrComplete ALUOp=Add ALUOp=Add ALUOp=Sub 1: BrWr, ExtOp ALUSelB=01 1: PCWr, IRWr beq x: IorD, Mem2Reg x: PCWrCond ALUSelB=10 x: RegDst, PCSrc RegDst, ExtOp RegDst, Mem2R IorD, MemtoReg 1: PCWrCond Others: 0s ALUSelA Others: 0s PCSrc lw or sw Ori Rtype 1: ExtOp LWmem AdrCal 1: RegDst RExec OriExec 1: ExtOp ALUSelA ALUOp=Or ALUSelA, IorD ALUSelA ALUSelB=01 1: ALUSelA ALUSelB=11 ALUSelB=11 ALUOp=Rtype ALUSelB=11 ALUOp=Add lw ALUOp=Add x: PCSrc, IorD x: MemtoReg x: MemtoReg MemtoReg x: MemtoReg PCSrc PCSrc ExtOp IorD, PCSrc sw Rfinish OriFinish LWwr 1: ExtOp SWMem 1: ALUSelA MemWr ALUOp=Rtype ALUOp=Or RegWr, ExtOp ALUSelA 1: RegDst, RegWr MemtoReg x: IorD, PCSrc ALUSelB=11 ALUselA ALUSelB=11 ALUOp=Add ALUSelB=11 ALUOp=Add ALUSelB=01 x: PCSrc,RegDst x: IorD, PCSrc 1: ALUSelA x: PCSrc MemtoReg IorD ExtOp RegWr ECE4680 Multipath.36 2002-3-31

19. Where to get more information? °Next two lectures: • Multiple Cycle Controller: Appendix C of your text book. • Microprogramming: Section 5.5 of your text book. °D. Patterson, “Microprograming,” Scientific America, March 1983. °D. Patterson and D. Ditzel, “The Case for the Reduced Instruction Set Computer,” Computer Architecture News 8, 6 (October 15, 1980) °Homework. See the website. ECE4680 Multipath.37 2002-3-31