RISC-V指令以及如何实现

1 .CS 61C: Great Ideas in Computer Architecture More RISC-V Instructions and How to Implement Functions Instructors: Krste Asanović and Randy H. Katz http://inst.eecs.Berkeley.edu/~cs61c /fa17 9/14/17 Fall 2017 - Lecture #6 1

2 .Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion … 9/14/17 2

3 .Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion … 9/14/17 3

4 .Levels of Representation/Interpretation lw x10 , 0 (x12 ) lw x11 , 4 (x12 ) sw x11 , 0 (x12 ) sw x10 , 4 (x12 ) High-Level Language Program (e.g., C) Assembly Language Program ( e.g., RISC-V) Machine Language Program (RISC-V) Hardware Architecture Description ( e.g., block diagrams) Compiler Assembler Machine Interpretation temp = v[k ]; v[k ] = v[k+1]; v[k+1] = temp; 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Architecture Implementation Anything can be represented as a number , i.e., data or instructions Logic Circuit Description (Circuit Schematic Diagrams) 9/14/17 4

5 .Review From Last Lecture … Computer “words” and “vocabulary” are called instructions and instruction set respectively RISC-V is example RISC instruction set used in CS61C Lecture/problems use 32-bit RV32 ISA, book uses 64-bit RV64 ISA Rigid format: one operation, two source operands, one destination add,sub,mul,div,and,or,sll,srl,sra lw,sw,lb,sb to move data to/from registers from/to memory beq , bne , j for decision/flow control Simple mappings from arithmetic expressions, array access, in C to RISC-V instructions 9/14/17 5

6 .Processor Control Datapath Recap: Registers live inside the Processor 6 PC Registers Arithmetic & Logic Unit (ALU) Memory Input Output Bytes Enable? Read/Write Address Write Data ReadData Processor-Memory Interface I/O-Memory Interfaces Program Data CS 61c

7 .Example if-else Statement Assuming translations below, compile f → x10 g → x11 h → x12 i → x13 j → x14 if ( i == j) bne x13,x14,Else f = g + h; add x10,x11,x12 else j Exit f = g – h; Else: sub x10,x11,x12 Exit: 9/14/17 7

8 .Magnitude Compares in RISC-V Until now, we’ve only tested equalities ( = = and != in C ); General programs need to test < and > as well. RISC-V magnitude-compare branches: “Branch on Less Than” Syntax : blt reg1,reg2 , label Meaning: if ( reg1 < reg2) // treat registers as signed integers goto label; “Branch on Less Than Unsigned” Syntax: bltu reg1,reg2, label Meaning: if (reg1 < reg2) // treat registers as unsigned integers goto label ; 9/14/17 8

9 .C Loop Mapped to RISC-V Assembly int A[20]; int sum = 0; for ( int i =0; i <20; i ++) sum += A[ i ]; addi x9, x8, 0 # x9=&A[0] addi x10, x0, 0 # sum=0 addi x11, x0, 0 # i =0 Loop: lw x12, 0(x9) # x12=A[ i ] add x10,x10,x12 # sum+= addi x9,x9,4 # &A[ i ++] addi x11,x11,1 # i ++ addi x13,x0,20 # x13=20 blt x11,x13,Loop 9

10 .Peer Instruction Which of the following is TRUE? RED : add x10,x11,4(x12) is valid in RV32 GREEN : can byte address 8GB of memory with an RV32 word ORANGE : imm must be multiple of 4 for lw x10,imm(x10) to be valid YELLOW : None of the above 9/14/17 10

11 .Peer Instruction Which of the following is TRUE? RED : add x10,x11,4(x12) is valid in RV32 GREEN : can byte address 8GB of memory with an RV32 word ORANGE : imm must be multiple of 4 for lw x10,imm(x10) to be valid YELLOW : None of the above 9/14/17 11

12 .Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion … 9/14/17 12

13 .Assembler to Machine Code (more later in course) foo.S bar.S Assembler Assembler foo.o bar.o Linker lib.o a.out Assembler source files (text) Machine code object files Pre-built object file libraries Machine code executable file A ssembler converts human-readable assembly code to instruction bit patterns 9/14/17 13

14 .How Program is Stored Memory Bytes Program Data One RISC-V Instruction = 32 bits 9/14/17 14

15 .Processor Control Datapath Program Execution PC Registers Arithmetic & Logic Unit (ALU) Memory Bytes Instruction Address Read Instruction Bits Program Data PC (program counter) is internal register inside processor holding byte address of next instruction to be executed Instruction is fetched from memory, then control unit executes instruction using datapath and memory system, and updates program counter (default is add +4 bytes to PC , to move to next sequential instruction) 9/14/17 15

16 .In the News: Why fast computers matter CS 61c 16 European Weather supercomputer ECMWF 50 tonnes ~120,000 compute cores (Intel Broadwell ) 10 PetaBytes of storage Runs Linux on each node

17 .Break! 9/14/17 17

18 .Helpful RISC-V Assembler Features Symbolic register names E.g., a 0-a7 for argument registers ( x10-x17 ) E.g., zero for x0 Pseudo-instructions Shorthand syntax for common assembly idioms E.g., mv rd , rs = addi rd , rs , 0 E.g .2, li rd , 13 = addi rd , x0, 13 18

19 .RISC-V Symbolic Register Names 19 Numbers hardware understands Human-friendly symbolic names in assembly code

20 .Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion … 9/14/17 20

21 .Six Fundamental Steps in Calling a Function Put parameters in a place where function can access them Transfer control to function Acquire (local) storage resources needed for function Perform desired task of the function Put result value in a place where calling code can access it and restore any registers you used Return control to point of origin, since a function can be called from several points in a program 9/14/17 21

22 .RISC-V Function Call Conventions Registers faster than memory, so use them a0–a7 ( x10-x17 ) : eight argument registers to pass parameters and two return values ( a0-a1 ) ra : one return address register to return to the point of origin ( x1 ) 9/14/17 22

23 .Instruction Support for Functions (1/4) ... sum(a,b );... /* a,b :s0,s1 */ } int sum( int x, int y) { return x+y ; } address (shown in decimal) 1000 1004 1008 1012 1016 … 2000 2004 C RISC-V In RISC-V, all instructions are 4 bytes, and stored in memory just like data. So here we show the addresses of where the programs are stored. 9/14/17 23

24 .Instruction Support for Functions (2/4) ... sum(a,b );... /* a,b :s0,s1 */ } int sum( int x, int y) { return x+y ; } address (shown in decimal) 1000 mv a0,s0 # x = a 1004 mv a1,s1 # y = b 1008 addi ra,zero , 1016 # ra =1016 1012 j sum # jump to sum 1016 … # next instruction … 2000 sum : add a 0,a0,a1 2004 jr ra # new instr. “jump register” 9/14/17 24 C RISC-V

25 .Instruction Support for Functions ( 3/4) ... sum(a,b );... /* a,b :s0,s1 */ } int sum( int x, int y) { return x+y ; } 2000 sum: add a 0,a0,a1 2004 jr ra # new instr. “jump register” Question: Why use jr here ? Why not use j ? Answer: sum might be called by many places, so we can’t return to a fixed place. The calling proc to sum must be able to say “return here” somehow. 9/14/17 25 C RISC-V

26 .Instruction Support for Functions ( 4/4) Single instruction to jump and save return address: jump and link ( jal ) Before : 1008 addi ra,zero ,1016 # ra =1016 1012 j sum # goto sum After : 1008 jal sum # ra =1012,goto sum Why have a jal ? Make the common case fast: function calls very common Reduce program size Don’t have to know where code is in memory with jal ! 9/14/17 26

27 .RISC-V Function Call Instructions Invoke function : jump and link instruction ( jal ) (really should be laj “link and jump” ) “link” means form an address or link that points to calling site to allow function to return to proper address Jumps to address and simultaneously saves the address of the following instruction in register ra jal FunctionLabel Return from function : jump register instruction ( jr ) Unconditional jump to address specified in register: jr ra Assembler shorthand: ret = jr ra 9/14/17 27

28 .Outline RISC-V ISA and C-to-RISC-V Review Program Execution Overview Function Call Function Call Example And in Conclusion … 9/14/17 28

29 .Example int Leaf (int g, int h, int i , int j) { int f ; f = ( g + h ) – ( i + j ); return f ; } Parameter variables g , h , i , and j in argument registers a0 , a1 , a2 , and a3 , and f in s0 Assume need one temporary register s1 9/14/17 29