# 05计算机组成--分支指令

1.Various branch instructions beq \$6, \$8, there (branch if equal) bne \$6, \$8, here (branch if not equal) j label {unconditional branch to label} jr \$6 {branch to the address stored in \$6} Which format do these instruction use? Instructions for comparison slt \$1, \$2, \$3 (set less than) If r2 < r3 then r1:=1 else \$r1:=0 There is a pseudo-instruction blt \$s0, \$s1, label The assembler translates this to the following: slt \$t0, \$s0, \$s1 # if \$s0 < \$s1 then \$t0 =1 else \$t0 = 0 bne \$t0, \$zero, label # if \$t0 ≠ 0 then goto label

2.Compiling a switch statement switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g – h; break; case 3: f = i – j; break; } Assume, \$s0-\$s5 contain f, g, h, i, j, k. Let \$t2 contain 4. {Check if k is within the range 0-3} slt \$t3, \$s5, \$zero # if k < 0 then \$t3 = 1 else \$t3=0 bne \$t3, \$zero, Exit # if k<0 then Exit slt \$t3, \$s5, \$t2 # if k<4 then \$t3 = 1 else \$t3=0 beq \$t3, \$zero, Exit # if k≥ 4 the Exit Exit: What next? Jump to the right case!

3. Base address 32-bit address L0 of the jumptable 32-bit address L1 jumptable 32-bit address L2 register \$t4 32-bit address L3 f=i+j L0 J Exit f = g+h L1 j Exit Exit MEMORY