短沟道效应

短沟道效应:缓变沟道的近似不再成立,这个二维电势分布会导致阈值电压随L的缩短而下降,亚阈值特征的降级以及由于隧穿穿透效应而使电流饱和失效,在沟道出现二维电势分布以及高电场,这些不同于长沟道MOS场效应晶体管特性的现象,统称为短沟道效应。沟道长度减小到一定程度后,源、漏结的耗尽区在整个沟道中所占的比重增大,栅下面的硅表面形成反型层所需的电荷量减小,因而阈值电压减小。
展开查看详情

1. Lecture #27 ANNOUNCEMENTS • Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( βdc> 45, fT > 18 GHz, VA > 9 V and Vpunchthrough > 9 V ) OUTLINE • Short channel effect • Drain-induced barrier lowering • Excess current effects • Parasitic source/drain resistance Spring 2003 EE130 Lecture 26, Slide 1 The Short Channel Effect (SCE) “VT roll-off” • |VT| decreases with L – Effect is exacerbated by high values of |VDS| • This is undesirable (i.e. we want to minimize it!) because circuit designers would like VT to be invariant with transistor dimensions and biasing conditions Spring 2003 EE130 Lecture 26, Slide 2 1

2. Qualitative Explanation of SCE • Before an inversion layer forms beneath the gate, the surface of the Si underneath the gate must be depleted (to a depth Wdm) • The source & drain pn junctions assist in depleting the Si underneath the gate – Portions of the depletion charge in the channel region are balanced by charge in S/D regions, rather than by charge on the gate ⇒ less gate charge is required to reach inversion (i.e. |VT | decreases) Spring 2003 EE130 Lecture 26, Slide 3 The smaller the L, the greater percentage of charge balanced by the S/D pn junctions: depletion charge supported VG by gate (simplified rj n+ n+ analysis) p depletion region Large L: Small L: S D S D Depletion charge Depletion charge supported by S/D supported by S/D Spring 2003 EE130 Lecture 26, Slide 4 2

3. First-Order Analysis of SCE • The gate supports the depletion charge in the trapezoidal region. This is smaller than the rectangular depletion region Wdm underneath the gate, by the factor ′ L+L 1− 2L • This is the factor by which the depletion charge Qdep is reduced from the ideal • One can deduce from simple   2Wdm geometric analysis that L′ = L − 2 rj  1 + − 1  rj  Spring 2003 EE130 Lecture 26, Slide 5 VT Roll-Off: First-Order Model − qN AWdm rj  2Wdm  VT − VT ( long − channel ) ≡ ∆ VT = 1+ − 1 Coxe L  rj   Minimize ∆VT by Wdm • reducing Toxe • reducing rj • increasing NA (trade-offs: degraded m, µ) ⇒ MOSFET vertical dimensions should be scaled along with horizontal dimensions! Spring 2003 EE130 Lecture 26, Slide 6 3

4. Source and Drain Structure • To minimize SCE, we want shallow (small rj) S/D regions -- but the parasitic resistance of these regions will increase when rj is reduced. Rsource , Rdrain ∝ ρ / Wrj where ρ = resistivity of the S/D regions • Shallow S/D “extensions” may be used to effectively reduce rj without increasing the S/D sheet resistance too much Spring 2003 EE130 Lecture 26, Slide 7 Electric Field Along Channel • The lateral electric field peaks at the drain. – Epeak can be as high as 106 V/cm • High E-field causes several problems: – impact ionization Æ substrate current – damage to gate-oxide interface and bulk Spring 2003 EE130 Lecture 26, Slide 8 4

5. Lightly Doped Drain Structure • Lower pn junction doping results in lower peak E-field 9 Hot-carrier effects reduced 8 Series resistance increased Spring 2003 EE130 Lecture 26, Slide 9 Parasitic Source-Drain Resistance contact metal dielectric spacer G gate oxide Rs Rd S D channel N+ source or drain CoSi2 or TiSi2 I Dsat 0 • If IDsat0 ∝ VGS – VT , I Dsat = I R 1 + Dsat 0 s (VGS − VT ) • IDsat is reduced by about 15% in a 0.1µm MOSFET. • VDsat = VDsat0 + IDsat (Rs + Rd) Spring 2003 EE130 Lecture 26, Slide 10 5

6.Drain Induced Barrier Lowering (DIBL) • As the source & drain get closer, they become electrostatically coupled, so that the drain bias can affect the potential barrier to carrier flow at the source junction Æ subthreshold current increases. Spring 2003 EE130 Lecture 26, Slide 11 Excess Current Effects • Punchthrough Spring 2003 EE130 Lecture 26, Slide 12 6

7. • Parasitic BJT action Spring 2003 EE130 Lecture 26, Slide 13 Summary: MOSFET OFF State vs. ON State • Sub-threshold regime (VGS < VT): – IDS is limited by the rate at which carriers diffuse across the source pn junction – Subthreshold swing S, DIBL are issues • ON state (VGS > VT): – IDS is limited by the rate at which carriers drift across the channel – Punchthrough and parasitic BJT effects are of concern, particularly at high drain bias • IDsat increases rapidly with VDS – Parasitic series resistances reduce drive current • source resistance RS reduces effective VGS • source and drain resistances RS and RD reduce effective VDS Spring 2003 EE130 Lecture 26, Slide 14 7

8.Spring 2003 EE130 Lecture 26, Slide 15 8