1.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 1 Topic 9 MOS Memory and Storage Circuits ECE 271 Electronic Circuits I

2.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 2 Chapter Goals Overall memory chip organization Static memory circuits using the six-transistor cell Dynamic memory circuits Sense amplifier circuits used to read data from memory cells Learn about row and address decoders Implementation of CPU registers via flip-flops Pass transistor logic Read Only Memory

3.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 3 Memory Types Read Only Memory (ROM) refers to memory in a digital system that has only read capabilities. Can be used to perform logic operations. Random Access Memory (RAM) refers to memory in a digital system that has both read and write capabilities. Mostly it’s a high speed temporary storage memory. Static RAM (SRAM) is able to store its information as long as power is applied, and it does not lose the data during a read cycle (early memory was mostly SRAM) Dynamic RAM (DRAM) uses a capacitor to temporarily store data which must be refreshed periodically to prevent information loss, and the data is lost in most DRAMs during the read cycle SRAM takes approximately four times the silicon area of DRAM with the same technology. Digital systems also include usually high speed small size memory – registers to temporarily store information used in operations. The memory chip usually includes the storage cells , address decoders - logical circuits for selecting and accessing a particular cell, and sense amplifiers for amplifying the signal retrieved from a cell.

4.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 4 Static Memory Cells There are two types of basic electronic storage elements – latch and flip-flop.

5.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 5 Static Memory Cells There are two types of basic electronic storage elements – latch and flip-flop. The latch - a memory cell built from two feedback connected inverters Latch

6.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 6 Static Memory Cells There are two types of basic electronic storage elements – latch and flip-flop. The latch - a memory cell built from two feedback connected inverters The set-reset flip-flop (RS-FF) - a memory cell built from two feedback connected NOR or NAND gates. Latch Flip-Flop

7.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 7 Static Memory Cells There are two types of basic electronic storage elements – latch and flip-flop. The latch - a memory cell built from two feedback connected inverters The set-reset flip-flop (RS-FF) - a memory cell built from two feedback connected NOR or NAND gates. The circuits use positive feedback to store information. Latch Flip-Flop

8.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 8 Static Memory Cells There are two types of basic electronic storage elements – latch and flip-flop. The latch - a memory cell built from two feedback connected inverters The set-reset flip-flop (RS-FF) - a memory cell built from two feedback connected NOR or NAND gates. These circuits use positive feedback to store information. These circuits have two stable states – bistable circuits . Latch Flip-Flop

9.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 9 Latch Static Memory Cell The behavior of the cell can be understood by analyzing its VTC . 3

10.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 10 Latch Static Memory Cell The behavior of the cell can be understood by analyzing its VTC. Blue curve is the VTC of the two cascaded inverters 1 and 2. 3

11.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 11 Latch Static Memory Cell The behavior of the cell can be understood by analyzing its VTC. Blue curve is the VTC of the two cascaded inverters 1 and 2. The red line (slope=1) is the VTC of the unit feedback 3. 3

12.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 12 Latch Static Memory Cell The equilibrium operating points are given by the intersection of the two VTC curves. The behavior of the cell can be understood by analyzing its VTC. Blue curve is the VTC of the two cascaded inverters 1 and 2. The red line (slope=1) is the VTC of the unit feedback 3. 3

13.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 13 Latch Static Memory Cell The equilibrium operating points are given by the intersection of the two VTC curves. There are two stable Q-points : v I = v O = v H and v I = v O = v L . Small deviations from those two points will cause the cell to return into themselves. The behavior of the cell can be understood by analyzing its VTC. Blue curve is the VTC of the two cascaded inverters 1 and 2. The red line (slope=1) is the VTC of the unit feedback 3. 3

14.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 14 Latch Static Memory Cell The equilibrium operating points are given by the intersection of the two VTC curves. There are two stable Q-points : v I = v O = v H and v I = v O = v L . Small deviations from those two points will cause the cell to return into themselves. There is also one unstable Q-point in the middle, where slight changes in the voltage will cause it to latch in one of the stable states The behavior of the cell can be understood by analyzing its VTC. Blue curve is the VTC of the two cascaded inverters 1 and 2. The red line (slope=1) is the VTC of the unit feedback 3. 3

15.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 15 The 6-T Cell The previous cell can exist indefinitely long in one of the stable states – high or low, i.e. it can store one bit of information – 0 or 1. However this construction is not yet usable because there is no mechanism to change the state - to “write” the information into sell.

16.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 16 The 6-T Cell The previous cell can exist indefinitely long in one of the stable states – high or low, i.e. it can store one bit of information – 0 or 1. However this construction is not yet usable because there is no mechanism to change the state - to “write” the information into sell. This is accomplished by addition of two control (access) transistors  a called 6-T (6 transistor) cell that can store 0 and 1values of the data and allows to “write” and to “read” that data. The access transistors also isolate one cell from another in a memory array.

17.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 17 The 6-T Cell The previous cell can exist indefinitely long in one of the stable states – high or low, i.e. it can store one bit of information – 0 or 1. However this construction is not yet usable because there is no mechanism to change the state - to “write” the information into sell. This is accomplished by addition of two control (access) transistors  a so called 6-T (6 transistor) cell that can store 0 and 1values of the data and allows to “write” and to “read” that data. The access transistors also isolate one cell from another in a memory array. Substituting the inverters with their CMOS representation, we obtain the circuit implementation of the 6-T SRAM cell.

18.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 18 The Read Operation of a 6-T Cell Consider a 6-T cell with V DD = 3V.

19.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 19 The Read Operation of a 6-T Cell Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node

20.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 20 The Read Operation of a 6-T Cell Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2

21.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 21 The Read Operation of a 6-T Cell Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2 A “1” in the memory cell corresponds to a high level on D 1 , and a low level on D 2 .

22.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 22 The Read Operation of a 6-T Cell “0” WL=0 WL=0 Initial state of the cell storing a “0” with the bitlines ’ initially precharged to V DD /2 and WL set to 0. Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2 A “1” in the memory cell corresponds to a high level on D 1 , and a low level on D 2 .

23.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 23 The Read Operation of a 6-T Cell WL=0 WL=0 Initial state of the cell storing a “0” with the bitlines ’ initially precharged to V DD /2 and WL set to 0. WL=0 WL=0 “0” “0” Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2 A “1” in the memory cell corresponds to a high level on D 1 , and a low level on D 2 .

24.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 24 The Read Operation of a 6-T Cell To read the data we set WL to 3V, Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2 A “1” in the memory cell corresponds to a high level on D 1 , and a low level on D 2 . WL=0 WL=0 Initial state of the cell storing a “0” with the bitlines ’ initially precharged to V DD /2 and WL set to 0. “0” “0”

25.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 25 The Read Operation of a 6-T Cell WL=0 WL=0 Initial state of the cell storing a “0” with the bitlines ’ initially precharged to V DD /2 and WL set to 0. To read the data we set WL to 3V, which sets WL transistors ON: M A1 – in triode ( V GS = ? , V DS = ? ), Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2 . A “1” in the memory cell corresponds to a high level on D 1 , and a low level on D 2 . “0” “0”

26.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 26 The Read Operation of a 6-T Cell WL=0 WL=0 Initial state of the cell storing a “0” with the bitlines ’ initially precharged to V DD /2 and WL set to 0. To read the data we set WL to 3V, which sets WL transistors ON: M A1 – in triode ( V GS = 3 , V DS = 1.5 ), i 1 goes from bitline to cell Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2 . A “1” in the memory cell corresponds to a high level on D 1 , and a low level on D 2 . “0” “0”

27.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 27 The Read Operation of a 6-T Cell WL=0 WL=0 Initial state of the cell storing a “0” with the bitlines ’ initially precharged to V DD /2 and WL set to 0. To read the data we set WL to 3V, which sets WL transistors ON: M A1 – in triode ( V GS =3, V DS =1.5), i 1 goes from bitline to cell M A2 – in saturation ( V GS = ? , V DS = ? ), Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2 . A “1” in the memory cell corresponds to a high level on D 1 , and a low level on D 2 . “0” “0”

28.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 28 The Read Operation of a 6-T Cell WL=0 WL=0 Initial state of the cell storing a “0” with the bitlines ’ initially precharged to V DD /2 and WL set to 0. To read the data we set WL to 3V, which sets WL transistors ON: M A1 – in triode ( V GS =3, V DS =1.5), i 1 goes from bitline to cell M A2 – in saturation ( V GS = 1.5 , V DS = 1.5 ), i 2 goes from cell to bitline Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2 . A “1” in the memory cell corresponds to a high level on D 1 , and a low level on D 2 . “0” “0”

29.NJIT ECE 271 Dr. Serhiy Levkov Topic 9 - 29 The Read Operation of a 6-T Cell WL=0 WL=0 Initial state of the cell storing a “0” with the bitlines ’ initially precharged to V DD /2 and WL set to 0. To read the data we set WL to 3V, which sets WL transistors ON: M A1 – in triode ( V GS =3, V DS =1.5), i 1 goes from bitline to cell M A2 – in saturation ( V GS =1.5, V DS =1.5), i 2 goes from cell to bitline Currents i 1 and i 2 are sensed by sense amplifier, which helps to set BL to 0V and BL to 3V. Consider a 6-T cell with V DD = 3V. Assume that A “0” in the memory cell corresponds to a low level (0V) on the left data storage node D 1 , and a high level (3V) on the right data node D 2 . A “1” in the memory cell corresponds to a high level on D 1 , and a low level on D 2 . “0” “0”