Combinational Logic Circuits
-Graphic Symbols (IEEE and IEC)
-Switching Circuits
-Analyzing IC Logic Circuits
-Designing IC Logic Circuits
-Detailed Schematic Diagrams
-Using Equivalent Symbols

low_key发布于2019/01/29

1.Lecture 6 Topics Combinational Logic Circuits Graphic Symbols (IEEE and IEC) Switching Circuits Analyzing IC Logic Circuits Designing IC Logic Circuits Detailed Schematic Diagrams Using Equivalent Symbols 1

2.Combinational Logic Circuits Combinational Logic Outputs depend only upon the current inputs (not previous “state”) Positive Logic High voltage ( H ) represents logic 1 (“True”) “Signal BusGrant is asserted High” Negative Logic Low voltage ( L ) represents logic 1 (“True”) “Signal BusRequest # is asserted Low” 2

3.Graphic Symbols

4.IEEE: Institute of Electrical and Electronics Engineers IEC: International Electro- technical Commission 4

5.5

6.6

7.Pass Logic versus Regenerative Logic

8.n.o . = normally open n.c. = normally closed 8 These regenerative logic switching circuits that we’ll be seeing are actually very close to the way real CMOS ICs are implemented and can be a useful model for us without getting into the details of how the transistors actually work. In particular, note the voltage differential and direction of current flow! OR gate using Pass Logic and using Regenerative Logic

9.9 AND gate using Pass Logic and using Regenerative Logic n.o . = normally open n.c. = normally closed

10.10 NOT gate using Pass Logic and using Regenerative Logic n.o . = normally open n.c. = normally closed

11.11 NOR gate using Pass Logic and using Regenerative Logic n.o . = normally open n.c. = normally closed

12.12 NAND gate using Pass Logic and using Regenerative Logic n.o . = normally open n.c. = normally closed

13.13 Buffer gate using Pass Logic and using Regenerative Logic n.o . = normally open n.c. = normally closed

14.14 XOR gate using Pass Logic and using Regenerative Logic n.o . = normally open n.c. = normally closed

15.15 XNOR gate using Pass Logic and using Regenerative Logic n.o . = normally open n.c. = normally closed

16.All Possible Two-Variable Functions

17.All Possible Two Variable Functions Question: How many unique functions of two variables are there? Recall earlier question… 17

18.Truth Tables B 5 B 4 B 3 B 2 B 1 B 0 F 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 . . . 1 1 1 1 1 1 1 0 1 2 3 . . . 63 2 6 = 64 Question: How many rows are there in a truth table for n variables? As many rows as unique combinations of inputs Enumerate by counting in binary 2 n 18

19.Two Variable Functions Question: How many unique combinations of 2 n bits? Enumerate by counting in binary 2 2 n 2 64 19 B 5 B 4 B 3 B 2 B 1 B 0 F 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 . . . 1 1 1 1 1 1 1 0 1 2 3 . . . 63 2 6 = 64

20.All Possible Two Variable Functions Question: How many unique functions of two variables are there? B 1 B 0 F 0 0 0 0 1 1 1 0 1 1 1 0 2 2 = 4 rows 4 bits Number of unique 4 bit words = 2 4 = 16 20

21.21

22.Analyzing Logic Circuits

23.Analyzing Logic Circuits Reference Designators (“Instances”) X + Z X X + Y (X + Y) × (X + Z) 23

24.Analyzing Logic Circuits C A × B B × C A × B + B × C 24

25.Another example

26.Designing Logic Circuits

27.Designing Logic Circuits F1 = A × B × C + B × C + A × B SOP form with 3 terms  3 input OR gate 27

28.Designing Logic Circuits F1 = A × B × C + B × C + A × B Complement already available 28

29.Some Terminology F1 = A × B × C + B × C + A × B Signal line – any “wire” to a gate input or output 29

30.Some Terminology F1 = A × B × C + B × C + A × B Net – collection of signal lines which are connected 30

31.Some Terminology F1 = A × B × C + B × C + A × B Fan-out – Number of inputs an IC output is driving Fan-out of 2 31

32.Some Terminology F1 = A × B × C + B × C + A × B Fan-in – Number of inputs to a gate Fan-in of 3 32 Book confused “fan-out” with “maximum fan-out”

33.Vertical Layout Scheme – SOP Form 33

34.Vertical Layout Scheme – SOP Form 34

35.&gt;2 Input OR Gates Not Available for all IC Technologies Solution: “Cascading” gates 35

36.Vertical Layout Scheme – POS Form F2 = (X+Y) ×( X+Y) ×( X+Z) 36

37.Designing Using DeMorgan Equivalents Often prefer NAND/NOR to AND/OR when using real ICs NAND/NOR typically have more fan-in NAND/NOR “functionally complete” NAND/NOR usually faster than AND/OR 37

38.NAND and NOR gates

39.AND/OR forms of NAND DeMorgan’s Theorem 39

40.Summary of AND/OR forms Change OR to AND “Complement” bubbles 40

41.Equivalent Signal Lines 41

42.NAND/NAND Example 42

43.NOR/NOR Example 43

44.44

46.Duality Swap 0 &amp; 1, AND &amp; OR Result: Theorems still true Why? Each axiom (A1-A5) has a dual (A1 ¢ -A5 ¢) Counterexample: X + X × Y = X (T9) X × X + Y = X (dual) X + Y = X (T3 ¢ ) ???????????? X + (X × Y) = X (T9) X × (X + Y) = X (dual) (X × X) + (X × Y) = X (T8) X + (X × Y) = X (T3 ¢ ) parentheses, operator precedence!

47.N-variable Theorems Prove using finite induction Most important: DeMorgan theorems

48.DeMorgan Symbol Equivalence

49.Likewise for OR (be sure to check errata!)

50.DeMorgan Symbols

51.Three Methods of analysis of combinational Circuits

52.Combinational analysis

53.Signal expressions Multiply out: F = ((X + Y ¢ ) × Z) + (X ¢ × Y × Z ¢ ) = (X × Z) + (Y ¢ × Z) + (X ¢ × Y × Z ¢ )

54.Signal Kmaps X’ 1 Y’ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 You perform Boolean operations on the whole Kmaps . OR- ing Kmap s

55.New circuit, same function

57.Shortcut: Symbol substitution

58.Different circuit, same function

59.Verification of solutions

60.Verification of your solutions helps you in most cases to avoid errors 60 Circuit Logic Expression Truth Table Karnaugh Map Optimized Logic Expression Optimized Circuit with AND , OR and NOT gates Optimized Circuit with NAND , NOR and NOT gates SYNTHESIS PROCESS

61.Verification of your solution is a reverse process 61 Circuit Logic Expression Truth Table Karnaugh Map Optimized Logic Expression Optimized Circuit with AND , OR and NOT gates Optimized Circuit with NAND , NOR and NOT gates BLUE ARROWS ARE SYNTHESIS PROCESS RED ARROWS ARE VERIFICATION PROCESS

62.Practical Example of Verification of a solution

63. 1 1 1 1 Given is an expression Z  X’Y. 1. Draw a Kmap . 2. Given the Karnaugh Map find circuit from AND, OR and NOT gates. 1 1 1 1 1 1 1 1 You find SOP = X’YZ’ + XZ + Y’Z You factorize SOP = X’YZ’ + Z(X + Y’) and get the circuit below. SYNTHESIS

64.X’ 1 Y’ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 You perform Boolean operations on the whole Kmaps . OR- ing Kmap s VERIFICATION 1. You start from circuit 2. You write equation for each gate Verification Method 1 Other verification Method 2 uses Kmaps for each gate. The result is a Kmap .

65.Verification of your solution is a reverse process to synthesis Circuit Logic Expression Karnaugh Map Optimized Logic Expression Optimized Circuit with AND , OR and NOT gates Optimized Circuit with NAND , NOR and NOT gates RED ARROWS ARE VERIFICATION METHODS Verification Method 1 created the expression for F Verification Method 2 created the Kmap for F Truth Table If required you create Truth Table from KMap If required you create logic equation of given style from KMap If required you create logic circuit of given style from KMap

66.You will increase your exam, quizz or homework scores if you will verify your solutions

67.Perkowski says, based on his own experience: 67 Clever Engineer verifies his/her solutions before showing them to her/his boss

68.68 Stupid Engineer does NOT verify his/her solutions before showing them to her/his boss and gets into troubles

69.Questions and Exam Problems(1) Draw and explain OR gate in pass transistor logic. Draw and explain AND gate in pass transistor logic. Draw and explain NOT gate in pass transistor logic . Draw and explain XOR gate in pass transistor logic. Draw and explain NAND gate in pass transistor logic. Draw and explain NOR gate in pass transistor logic. Draw and explain OR gate in regenerative logic . Draw and explain AND gate in regenerative logic . Draw and explain NOT gate in regenerative logic . Draw and explain XOR gate in regenerative logic . Draw and explain NAND gate in regenerative logic . Draw and explain NOR gate in regenerative logic. Difficult: how to realize all functions of two variables using multiplexers? How many MUX you need? What size? 69

70.Questions and EXAM Problems (2) 13. How to analyze SOP circuits? 14. How to analyze POS circuits? 15. How to verify your solutions to combinational logic circuits? 16. How to analyze arbitrary circuits with NAND,NOR and other gates and many levels? 17. How to realize SOP with NANDs? 18. How to realize SOP with NORs? 19. How to realize POS with NANDs? 20. How to realize POS with NORs ? 21. How to realize arbitrary logic circuit (schematics) with NANDs? 22. Show example of sharing subfunctions in a circuit that has only NAND gates. 23. Show example of sharing subfunctions in a circuit that has only NOR gates . 24. How to realize a circuit with AND, OR, NOT and EXOR operations using only NAND gates? 25. How to realize a circuit with AND, OR, NOT and EXOR operators using only XNOR and NAND gates? 70

71.Solution to the very difficult problem Supposedly solved by 4 students in 2014

72.ROLE OF INVERTERS IN MULTI-LEVEL CIRCUITS AND THE TWO-INVERTER PROBLEM ” . Before we proceed to synthesis with NAND and IMPLY gates let us consider the importance of negation in multi-output combinational logic. We solve the famous 2-Inverter problem. Problem Formulation. Assume that inverter is very expensive and AND and OR gates are for free. Given are two inverters only and an unlimited number of AND and OR gates. Synthesize a three-output function: FA = A ’ , FB = B ’ , FC = C ’ using only these gates. The reader is asked not to look to the solution below and try to solve this problem by himself. This problem is truly difficult and takes much time even from smart students. However, creating systematically Karnaugh Maps for all available functions allows to find a solution as in Figure 11.2.1. Thus we find: FA = A’ = Z’(B+C) + Z’F’ + F’(BC), FB = B’ = Z’(A+C) + Z’F’ + F’(AC), FC = C’ = Z’(A+B) + Z’F’ + F’(AB) A question however arrives: “ how the intermediate functions in Figure 11.2.1 were selected, as we can easily see that there are many more functions that can be created using two inverters and unlimited number of AND and ORs? ” One answer is = “ use symmetry, because problem is symmetric ” . But a better answer is to use the concept of “ dissected pairs ” which will be introduced below for practical synthesis with the minimum (or reduced) number of inverters. One more question to the reader: “ how to best generalize our results from Figure 11.2.1 above ? ” Getting some intuitions while solving this problem will help much the reader to understand methods from this and next chapters.

73.73 Figure 11.2.1. Step by step solution to the “ two inverter problem ” . FA = A’ = Z’(B+C) + Z’F’ + F’(BC), FB = B’ = Z’(A+C) + Z’F’ + F’(AC), FC = C’ = Z’(A+B) + Z’F’ + F’(AB)

74.A B FA = A’ = Z’(B+C) + Z’F’ + F’(BC), FB = B’ = Z’(A+C) + Z’F’ + F’(AC), FC = C’ = Z’(A+B) + Z’F’ + F’(AB) A C B C Z B C A C A B Z ’(B+C) Z’( A+C) Z ’(A+B) AB C F FA FB FC

75.Sources Prof. Mark G. Faust John Wakerly